Peta Hertz Clock based Peta bits per Second Speed PRBS- GPS HDL Transceiver Design for Ultra High Speed GPS Mobile Phone Computing System

Abstract

The Aim is for HDL Design & Implementation of PRBS Based GPS SOC Transceiver Design using VHDL & Verilog HDL. GPS SOC Transceiver contains Transmitter & Receiver and Transceiver SOC by Integration of Transmitter & Receiver. Transmitter Contains PRBS – Base Band Signal Navigation Data Generator with frequency of 50 Hz & Carrier Wave Generator with a frequency of 1.057 MHz and C(t) is Pseudo Random Code (C/A Code of Satellite is 1.023 MHz) . PRBS GPS Base Band Signal Generator & Carrier Wave Generator are XORed by using XOR Gate for generation of Digital Modulated Signal by Tapping Different Sequence Patterns 2e7-1,2e10-1,2e15-1,2e23-1,2e31-1 etc as per CCITT – ITU Standards (O.150,O.151,O.152) for Identification of Property of PRBS Modulated Signal codes and the same signal codes received by using PRBS GPS Receiver System and compared with the Received signal codes delayed with Transmitted one, and if the result is ‘0’ , no error in the received sequence. ‘1’ means error occurred in the received sequence. Speed of Transmission rate is in terms of Peta Bits Per Second Coding done by VHDL &/ Verilog HDL. Programming & Debugging Done by Xilinx ISE 9.2i Software Design Tool and Xilinx Spartan III FPGA Development Kit.